The present invention relates to fiber optic integrated circuit packages.
As the amount of functionality built into field programmable gate arrays (FPGAs) increases and as electronic systems increase in throughput and signaling speed, the amount of information flowing into and out of FPGAs has increased. It is envisioned that soon many FPGA devices will be input/output (I/O) limited or the operation of the FPGA devices will be hampered by inadequate capacity to get information into and out of the FPGA package. Future FPGA devices may be I/O limited both in terms of not having enough space at the periphery of the FPGA die to accommodate additional I/O functionality, and in terms of the speed of the on-chip I/O facilities being too slow to communicate the desired amount of information in the amount of time available.
FPGAs see increasing use in networking applications. A networking application may, for example, involve a printed circuit board that has a connector by which circuitry on the printed circuit board communicates with circuitry on a motherboard or main panel or back panel. Such a printed circuit board may, for example, be called a line card. One or more fiber optic connector jacks are typically provided on the optical line card. External fiber optic cables carrying network communications plug into the fiber optic connector jacks on the line card. Networking information flows from the fiber optic cable, through the fiber optic connector and onto the line card, through an optical-to-electrical transceiver on the line card, through other interface circuitry on the line card such as a serializer/deserializer (SERDES), and to the FPGA. In the other direction, information flows from the FPGA, through the SERDES, through an electrical-to-optical transceiver, through the fiber optic connector, and into the external fiber optic cable.
Typically each of the optical transceiver devices, the SERDES devices, and other intervening devices is packaged in its own package. These devices are therefore interconnected by relatively large electrical conductors and circuit board traces. High speed switching on these conductors in combination with the relatively large parasitic capacitance and inductances of these conductors results in an undesirably large amount of power consumption.
In addition to high power consumption, the design of the printed circuit board traces used to communicate information between these devices may be a daunting and time-consuming task for many FPGA users. High speed printed circuit board design can involve complex considerations and problems.
In addition to the difficulties associated with high speed printed circuit board design, disposing each of the various devices in its own separate package increases the aggregate packaging cost involved in realizing the system.
Not only are fiber optic communications desirable to interface an FPGA to a network such as in the line card example described above, but fiber optic communications are also desirable for other reasons. For example, there are situations where multiple large and high speed FPGAs are to be used together to realize a fairly complex system on a single printed circuit board. It may be desirable to communicate a large number of signals between these FPGAs at a high speed. The task of designing a great many high speed communication paths between the two FPGAs may be a difficult and time-consuming task. If a complex multi-layer printed circuit board is used for this purpose, the communication paths realized as traces on the printed circuit board are inflexible. If a path is to be changed, then a trace on the printed circuit board will have to be changed and the printed circuit board may have to be refabricated. The use of a printed circuit board to make large numbers of independent communication channels between such FPGAs is, therefore, be cumbersome. A solution to this problem is desired.
U.S. Pat. No. 6,364,542 illustrates an optoelectronic module that is fixed by an adhesive to the top of an integrated circuit package. The module contains optoelectronic devices such as, for example, a laser diode and a photodetector. The optoelectronic devices within the module communicate electrically with the central core of an integrated circuit in the package below via bond balls and associated posts that extend up from the integrated circuit in the package, through the integrated circuit package, through the base of the module, and to the optoelectronic devices. An external connector of a fiber optic cable snaps onto the module such that light from one fiber of the cable is transmitted onto the photodetector and such that light generated by the laser diode is transmitted to another fiber of the cable.
Although the package disclosed in U.S. Pat. No. 6,364,542 may be suitable for certain applications, fabrication and assembly of the integrated circuit package may be restrictively complex. If the clearance between the top of the integrated circuit die and the bottom inside surface of the package is too small, then the bond balls used to make contact with the integrated circuit may actually damage the integrated circuit die. If the clearance is too great, then adequate and repeatable contact between the bond balls and the integrated circuit may not be made. Moreover, the assembly involves placing the optoelectronic devices in a relatively small module and then electrically connecting the optoelectronic devices within the module to the integrated circuit die in the underlying integrated circuit package. This assembly introduces undesirable assembly steps and testing steps. It is desired that assembly of the complete package including a fiber optic connector be performed in a single controlled environment.
Not only is the assembly process complex, but the bond balls and posts used to connect the integrated circuit die to the optoelectronic die are large in comparison to the size of transistors and conductor lines on the integrated circuit die. Running high speed signals over the large bond balls and posts results in increased power consumption.
An improved package is desired.
A packaged FPGA integrated circuit includes a die-bonded assembly disposed within an integrated circuit package. The integrated circuit package includes a fiber optic connector that is connected to a cap portion of the integrated circuit package. A hermetically sealed chamber is formed when the cap portion is fitted onto a base portion of the integrated circuit package. The die-bonded assembly is disposed within this hermetically sealed chamber. The die-bonded assembly includes an optoelectronic die, the bottom surface of which is die-bonded to the upper surface of an FPGA integrated circuit die.
A first optical fiber extends in a direction substantially parallel to the plane of the upper surface of the FPGA die, from the fiber optic connector, through a first hole in the cap portion of the integrated circuit package, and to a reflecting surface. The reflecting surface reflects light exiting from the first optical fiber approximately ninety degrees such that the light is incident on a photodetector on the upper surface of the optoelectronic die. Accordingly, when an external fiber optic cable is snap fit onto the connector of the integrated circuit package, light passes from an optical fiber in the external cable, through the optical connector of the integrated circuit package, through the first optical fiber and to the reflecting surface. The light is reflected by the reflecting surface so that it is incident on the photodetector. The photodetector converts the light into an electrical signal. The electrical signal and/or information contained in the electrical signal is then communicated via small micropad structures from the optoelectronic die and down into the central core of the FPGA die.
A second optical fiber extends parallel to the first optical fiber through a second hole in the cap portion of the integrated circuit package. Information from the FPGA die is communicated via small micropad structures up to the optoelectronic die above. The information is converted into light by a light generating device (for example, a laser diode) disposed on the upper surface of the optoelectronic die. The light is emitted upward in a direction substantially perpendicular to the upper surface of the optoelectronic die, is reflected off the reflecting surface such that the light is redirected approximately ninety degrees and is incident on the second optical fiber. The light passes through the second optical fiber in a direction substantially parallel to the upper surface of the FPGA die, through the second hole in the cap portion of the integrated circuit package and to the fiber optic connector of the integrated circuit package. In the event the external fiber optic cable is snap fit onto the connector of the integrated circuit package, the light passes from the connector and into a second optical fiber of the fiber optic cable.
The packaged FPGA integrated circuit is advantageous in that it has a thin profile, low power consumption, and assembly-related advantages. These and other advantages are described in the detailed description below.
In a second embodiment, a low bend radius optical fiber is used as a waveguide between the fiber optic connector of the integrated circuit package and the optoelectronic die to both conduct light through a hole in the cap portion of the package as well as to change the propagation direction of the light approximately ninety degrees. No prism, lens, or reflecting surface on the cap portion is necessary in this embodiment.
In a third embodiment, the fiber optic connector is connected to the top surface of the cap portion such that an axial bore of a ferrule of the connector extends in a direction perpendicular to the upper surface of the optoelectronic die within the hermetically sealed chamber. A straight section of optical fiber extends from the ferrule of the connector, down through the cap portion of the package, and to the surface of the optoelectronic die. In this embodiment, there is no reflecting surface. Light passing through the optical fiber passes in a direction substantially perpendicular to the upper surface of the optoelectronic die.
In a fourth embodiment, an optoelectronic die is coupled to the FPGA die such that the upper surface of the optoelectronic die is disposed at a ninety degree angle with respect to the upper surface of the FPGA die. An optical fiber extends in a direction substantially parallel to the upper surface of the FPGA die from a fiber optic connector of the package, through a hole in a cap portion of the integrated circuit package, and to the optoelectronic die without being redirected ninety degrees by any reflecting surface or structure.
In a fifth embodiment, the photodetector and light generating devices of the optoelectronic die are edge-detecting and edge-transmitting devices, respectively. V-shaped grooves are etching into the upper surface of the optoelectronic die to align optical fibers to the edge-detecting and edge-transmitting devices.
In a sixth embodiment, a micromirror device is fixed to the inside surface of the cap portion of the integrated circuit package. Electrical signal conductors extend from the FPGA die, through the base portion of the package, up through the cap portion of the package, and to the micromirror device so that the micromirror device is controlled by the FPGA die. An optical fiber is used to direct light from a fiber optic connector of the package, through the wall of the cap portion, and to the micromirror device. The micromirror device focuses or directs light exiting the optical fiber onto the photodetector of the optoelectronic die. Similarly, the micromirror device is usable to focus or direct light emitted from a light generating device of the optoelectronic die onto a second optical fiber used to communicate light out of the integrated circuit package. This allows for misalignments between the optical fibers, micromirror device, and/or the optoelectronic device.
In a seventh embodiment, a multi-fiber bundle is extended into the integrated circuit package and a plurality of individual photodetectors are disposed on the optoelectronic die. The individual micromirrors of the micromirror device are used to establish a plurality of independent communication channels between the individual optical fibers of the bundle and the individual photodetectors of the optoelectronic die. The micromirror device is also usable as a splitter to direct part of the incoming light from the first optical fiber onto the optoelectronic part and part of the light back out of the package via the second optical fiber.
In an eighth embodiment, an array of photodetector/oscillators are distributed across the surface of the FPGA die. No optoelectronic die is provided. An optical fiber is used to communicate an optical clock signal from a fiber optic connector of the package to a plurality of micromirrors of a micromirror device, where the micromirror device is fixed to the inside of the cap portion of the package. Each of the micromirrors directs a portion of the optical clock signal onto a corresponding one of the photodetector/oscillators. The optical clock signal is received by the photodetector of a photodetector/oscillator and is converted into a corresponding electric signal. The electrical signal pumps an oscillator of the photodetector/oscillator such that the oscillator oscillates at the same frequency and in phase with each other photodetector/oscillator on the FPGA die. The oscillating signal of the oscillator is buffered and is then usable locally on the FPGA die in the area of the photodetector/oscillator. In this manner, a low-skew clock signal that is relatively jitter-free is distributed over the entire surface area of an FPGA die.
In a ninth embodiment, a laser diode is disposed at the apex of a pyramid-shaped FPGA integrated circuit package. An electrical clock signal is supplied onto a terminal of the package, and is directed up to the laser diode. The laser diode converts the electrical clock signal into an optical clock signal. The optical clock signal floods the interior hermetically-sealed chamber of the package such that the optical clock signal is incident on all the photodetector/oscillators on the upper surface of the FPGA die. A dispersing lens may be used to spread out the optical clock signal so that it floods the chamber. Each of the photodetector/oscillators receives the optical clock signal and outputs an electrical clock signal. The result is a low-skew electrical clock signal that is relatively jitter-free and is distributed over the entire surface area of the FPGA die.
A multiplexer is optionally disposed in the signal path between the FPGA die and the laser diode such that another signal can be selected to drive the laser diode. For example, a serial data signal can be received onto the packaged integrated circuit. A clock recovery circuit recovers a clock signal from a serial data signal. The recovered clock signal can then be selectively coupled by the multiplexer onto the conductor extending to the laser diode. Alternatively, an external crystal is coupled to an on-board oscillator. A clock signal generated by the on-board oscillator is selectively coupled by the multiplexer onto the signal path to the laser diode. Alternatively, an external crystal oscillator can be used to supply an electrical clock signal that drives the light generating device.
Other structures and methods are described in the detailed description below. This summary does not purport to define the invention. The invention is defined by the claims.